Tutorial Proposal ISCA 2026

SCALE-Sim Across the Silicon Lifecycle:

◆ [SCALE-Sim V3]   Pre-Silicon Cycle-Accurate Simulation for Next-Gen AI Accelerators
◆ [SCALE-Sim TPU] Post-Silicon Evaluation on State-of-the-art AI Accelerators
28 June 2026, Sunday Afternoon Session  ·  Half-Day Room 305A, Raleigh Convention Center, Raleigh, NC

Abstract

Modern design and simulation methodologies have led to design tools being increasingly used in the AI landscape — enabling rapid design-space exploration (DSE) and performance/power analysis to meet the demands of modern AI workloads. In this landscape, SCALE-Sim helps in designing next-gen AI accelerators through pre-silicon cycle-accurate full-system simulation and choosing AI models through post-silicon evaluation on state-of-the-art (SOTA) AI accelerators.

SCALE-Sim is used by over 100 organizations spanning academia, industry and govt labs. It has also received more than 500 GitHub stars. In this tutorial, we will present two major updates to the SCALE-Sim infrastructure.

Tutorial Overview

SCALE-Sim v3 Overview
Figure: Overview of SCALE-Sim v3 highlighting the new features over SCALE-Sim v2
SCALE-Sim TPU Validation Overview
Figure: SCALE-Sim TPU post-silicon evaluation on Google TPU v4 and TPU v6e

SCALE-Sim v3: Pre-Silicon

A modular, cycle-accurate simulator that extends v2 with five significant enhancements:

  • Multi-Core Simulation with Spatio-Temporal Partitioning
  • Sparse Matrix Multiplications (SpMM) with Layer- and Row-wise Sparsity
  • Ramulator Integration for Detailed DRAM Analysis
  • Precise Modeling of On-Chip Data Layout
  • Energy and Power estimation with Accelergy

SCALE-Sim TPU: Post-Silicon

Validated against measured on-device runtimes on Google TPU v4 and TPU v6e:

  • Regression analysis across diverse matrix sizes
  • Up to R² = 0.99 vs. measured TPU fusion-kernel runtimes
  • Supports Weight-Stationary (WS) and Input-Stationary (IS) dataflows
  • Cycle-level GEMM performance estimation for TPU-class architectures
  • Enables deployment studies for upcoming TPUv7 (Ironwood) systems

Schedule

Tentative — Subject to Change

Time Event Speaker Description
1:30 – 1:35 Introduction Dr. Tushar Krishna Introduce the vision behind the development of SCALE-Sim
1:35 – 2:15 Keynote Talk Dr. Suvinay Subramanian Keynote on Google TPUs
2:15 – 2:30 SCALE-Sim Talk Dr. Ananda Samajdar SCALE-Sim: From Intern Project to Global Collaboration
2:30 – 2:45 Overview of SCALE-Sim v3 Ritik Raj Overview of new features added to SCALE-Sim v3
2:45 – 3:00 Demo 1 — Accelergy Ritik Raj Understanding Compute-Memory Energy Breakdown
3:00 – 3:30 Demo 2 — Ramulator Dr. Sarbartha Banerjee Deep dive into on-chip and off-chip memory stalls for sparse cores
3:30 – 4:00 ☕ Coffee Break
4:00 – 4:15 Intro to SCALE-Sim TPU Jingtian Dang Post-silicon validation of SCALE-Sim to TPU-class architectures
4:15 – 4:40 Demo 3 — SCALE-Sim TPU Jingtian Dang Evaluating the performance of emerging workloads on Google TPU
4:40 – 4:50 Future Work Ritik Raj & Jingtian Dang Extensions and Future Development
4:50 – 4:55 Signing Off / Final Thoughts Dr. Tushar Krishna Open session with audience with future collaboration opportunities

Prior Offerings

This is the first iteration of the SCALE-Sim tutorial presenting SCALE-Sim v3 and SCALE-Sim TPU. Previous iterations using v2 of the simulator:

ASPLOS 2021 View Tutorial
ISCA 2021 View Tutorial

Organizers

Dr. Tushar Krishna
Dr. Tushar Krishna
Associate Professor,
Georgia Institute of Technology
Ritik Raj
Ritik Raj
Ph.D. Student,
Georgia Institute of Technology
Jingtian Dang
Jingtian Dang
Ph.D. Student,
Georgia Institute of Technology
Dr. Sarbartha Banerjee
Dr. Sarbartha Banerjee
Postdoctoral Fellow,
Georgia Institute of Technology

Invited Speakers

Dr.Suvinay Subramanian
Dr. Suvinay Subramanian
Computer Architect, Google
Dr. Ananda Samajdar
Dr. Ananda Samajdar
Research Staff Member, IBM T.J. Watson Research Center

Resources

Papers

  • J. Dang, R. Raj, C. Man, J. Tong, and T. Krishna. "SCALE-Sim TPU: Validating and Extending SCALE-Sim for TPUs." arXiv preprint arXiv:2603.22535, 2026.
  • R. Raj, S. Banerjee, N. Chandra, Z. Wan, J. Tong, A. Samajdar, and T. Krishna. "SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis." In 2025 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 186–200. IEEE, 2025.
  • A. Samajdar, J.M. Joseph, Y. Zhu, P. Whatmough, M. Mattina, T. Krishna. "A systematic methodology for characterizing scalability of DNN accelerators using SCALE-Sim." In 2020 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 58–68. IEEE, 2020.

Source Code

View on GitHub